Principal Design Verification Engineer – Digital - Semiconductors - Munich, Germany
- Job Title
- Principal Design Verification Engineer – Digital - Semiconductors - Munich, Germany
- Job ID
- 27393119
- Location
- Munich, Germany, BY
- Other Location
- Description
-
Our DACH client, a leading worldwide supplier of high performance optical sensors is in search of an:
Principal Design Verification Engineer – Digital - Semiconductors - Munich, GermanyTasks and responsibilities
- Member of the Design Verification Team in the Advanced Optical Solution division, working on mobile application IC's.
- Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
- Implementation of digital verification environments in conformance with internal and external engineering standards like UVM
- Analog behavior modelling, analog mixed mode simulations
- Definition and execution of state of the art digital methodologies, based on metric driven approaches
- Formal verification methods, DfT verification and power intend related verification
- SoC/IC verification, lab evaluation and test concept definition as core member of project team
- Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
- Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, etc
- Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
- Establish cross-correlation matrices for Verification/Evaluation/ATE results
- Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
Qualifications
- University degree in Electrical Engineering or similar
- Minimum 10 years professional experience since graduation
- Minimum 5 years of experience in the field of digital design verification
- Background in digital or analog IC circuit development, design for test and semiconductor technologies
- Proven expertise in handling state of the art EDA tools
- Good background in supporting processes like requirements engineering or configuration and change management and verification needs
- Experience in architecting and implementing UVM environment with strong focus on re-use
- Experience in programming languages (C, Verilog A and Cadence tools)
- Working knowledge of programming and scripting languages (C, Perl, Skill, Ocean, VerilogA/System Verilog)
- Candidate must be able to build test bench from scratch using UVM or System Verilog
- Demonstrated problem solving ability, analytical skills and laboratory proficiency
- Trained on design verification methodologies such as UVM, constraint random test generation
- Trained on developing verification environment and test cases, conducting functional simulations, writing bug management schemes
- Required Skills
-
University degree in Electrical Engineering or similar
10+ yrs industry work experience
5+ yrs exp in digital design verification
Bkgrnd in digital or analog IC circuit development, design for test and semiconductor technologies
EDA tools
requirements engineering/configuration and change management and verification needs
exp in architecting and implementing UVM environment
programming languages (C, Verilog A and Cadence tools)
programming and scripting languages (C, Perl, Skill, Ocean, VerilogA/System Verilog)
English fluency
EU citizen or German work permit holder
- Openings
- 1
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