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Analog/Mixed Signal Verification and Design Engineer

Job Title
Analog/Mixed Signal Verification and Design Engineer
Job ID
27356559
Location
Region St.Gallen, Switzerland,  SG
Other Location
Description

Your tasks and responsibilities

 

  • Responsible for planning & executing mixed-signal top-level IC verification for audio sensors
  • Develop test benches with high degree of automation
  • Implement mixed-signal behavioral models
  • Generate documentation for design verification planning & execution as well as customer reviews
  • Collaborate with digital verification engineers to achieve overall verification coverage
  • Support IC validation and production test (ATE) development
  • Ensure adoption of DV best practices, procedures and improvements within organization
  • Contribute to internal and external design & verification reviews

 

Your education and experiences

 

  • Degree in Electronic Engineering or related field
  • Knowledge in digital and mixed-signal design and verification
  • Experience with Cadence Designer and modelling in Verilog
  • Experience with Universal Verification Method (UVM) and modelling in System
  • Natural interest in EDA tools, persistent in solving software tool issues
  • Experience in verification coverage tracking
  • Programming skills in Linux shell, C, Perl and Tcl is an advantage
Required Skills

Structured and methodological approach
Strong team player
Excellent spoken and written communication skills in English
Openings
1

Option 1: Create a New Profile

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