|Job Title||Software / Systems Architect|
|Location||SANTA CLARA, CA 95054-1542|
In this role you will be responsible for system power and performance analysis, tuning, and debug products. As part of the team, you will collaborate closely with other Architects, Software Engineers, ASIC Design Engineers, and System Engineers to study, debug and implement the power consumption and performance of mobile chips in reference and customer designs.
- Validate the functionality and quantify the power savings and performance benefit of the features and algorithms implemented in our HW and SW.
- Perform measurements to characterize and tune the power and performance of reference platforms and next generation customer designs using real applications and usage models.
- Conduct directed studies and contribute solutions to functional power and performance challenges unique to mobile SOCs that are aimed at driving the architecture of next generation mobile products via measurements, simulations, benchmarking, or competitive analysis.
- Debug customer-visible system-level functional, power, and performance issues.
- MS in EE/CS/ECS or related technical field or equivalent. Ideal focus on computer architecture.
- 3 years or more of hardware and lab equipment experience including power measurement.
- 3 years or more of Perl or Python experience.
- Experience and familiarity with systems software, operating systems, as well as intuition for user level application interactions.
- Experience and familiarity with power management fundamentals, techniques, including leakage, clock gating, dynamic frequency and voltage scaling, and power sequencing.
- Experience in characterizing power and performance, doing comparison studies, and debugging power/performance issues.
- Experience with mobile power management ICs, voltage regulators, and board-level power delivery.
- Ability to distill questions about complex and concurrent systems into simple testable statements.
- ARM or other microprocessor experience.
- Video and/or 3D experience.
- Experience with chip backbone and interconnect architectures, buses, I/O hubs, I/O systems, storage, networking, media processing, etc.